According to a related art semiconductor manufacturing method, a process of forming an integrated semiconductor device includes forming a polysilicon/insulator/polysilicon (PIP) capacitor. FIG. 1 is a sectional view illustrating the problems according to the related art.
With the development of silicon semiconductor technologies, various methods have been introduced for integration of memory technology and logic technology. Memory technology generally performs data storing functions, and logic technology, such as that used to manufacture a central processing unit (CPU), a signal processor, etc., may perform data processing functions. Additionally, other technologies such as analog and radio frequency (RF) technologies can be integrated into logic and/or memory technologies.
Various devices such as transistors, capacitors, and resistors can be integrated into a chip or other semiconductor device to form a semiconductor integrated circuit (IC). Various methods have been developed for efficiently integrating such devices. An analog capacitor, such as a polysilicon/insulator/polysilicon (PIP) capacitor or a metal/insulator/metal (MIM) capacitor, is mainly used for a logic circuit, such as a complementary metal oxide semiconductor (CMOS) logic circuit.
The PIP capacitor is widely used for an analog device to prevent noise and perform frequency modulation. FIG. 1 is a cross-sectional view illustrating a semiconductor device including a PIP capacitor and a logic circuit according to the related art. In FIG. 1, A denotes a resistor region, B denotes a capacitor region, and C denotes a logic transistor region.
Referring to FIG. 1, a device isolation layer 3 is formed in a silicon substrate 1 to define an active region. A resistor 7 is formed in the resistor region A of the silicon substrate 1. A PIP capacitor is formed in the capacitor region B. The PIP capacitor includes a bottom electrode 9, a dielectric layer 13, and a top electrode 15.
Metal oxide semiconductor (MOS) transistors are formed in the logic transistor region C. Each of the MOS transistors include a gate insulation layer 5 formed on the silicon substrate 1, a gate electrode 11 formed on the gate insulation layer 5, and source and drain regions 10 formed adjacent to the gate electrode 11 in the active region defined by the device isolation layer 3.
First and second interlayer insulation layers 17 and 19 are formed on the silicon substrate 1 to cover the resistor 7, the PIP capacitor, and the MOS transistors. Contact plugs 21 and 25 are formed through the first and second interlayer insulation layers 17 and 19. The contact plugs 21 and 25 are connected to the PIP capacitor and the MOS transistors. Metal lines 27 are then formed to connect the contact plugs 21 and 25.
In the semiconductor device shown in FIG. 1, the capacitance of the PIP capacitor is determined by the area of the dielectric layer 13 formed between the bottom and top electrodes 9 and 15.
By reducing the number of process steps to produce a semiconductor device that includes a PIP capacitor, as described above (e.g., an IC), a more efficient fabrication and a device with improved characteristics can be achieved. Additionally, the device could be fabricated with less concern for the PIP thermal budget.